Method of fabricating and integrated circuit through utilizing metal layers to program randomly positioned basic units

ABSTRACT

A method of fabricating an integrated circuit. The integrated circuit has a semiconductor body. The method includes forming a plurality of basic units with the same component characteristic on the semiconductor body, and forming at least a layout layer to program the basic units for building a clocked logic circuit and a non-clocked logic circuit without placing restrictions on positions of the clocked logic circuit and the non-clocked logic circuit on the semiconductor body.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a metal programmable integrated circuit, and more specifically, to a method of fabricating an integrated circuit through utilizing metal layers to program randomly positioned basic units.

2. Description of the Prior Art

FIG. 1 is a diagram showing a prior art semiconductor body 10 of an integrated circuit. The semiconductor body has a plurality of functional circuit cells 12. The functional circuit cells 12 are arranged row-by-row or column-by-column according to an array format to finally form a matrix format. It is well-known that the matrix format corresponds to a minimum chip size. That is, the allocation of the functional circuit cells 12 corresponds to a maximum component density.

The semiconductor body 10 is divided into synchronous regions 14 a, 14 b and a non-synchronous region 16. All of the functional circuit cells 18 a, 18 b within the synchronous regions 14 a, 14 b operate according to a clock signal. For example, each of the functional circuit cells 18 a, 18 b respectively functions as a flip-flop, a latch, or a clock buffer after being defined by a corresponding routing design. On the other hand, the functional circuit cells 20 within the non-synchronous region 16 are not driven by clock signals.

Each functional circuit cell 20 is capable of performing a predetermined logic operation after being defined by a corresponding routing design. For example, each of the functional circuit cells 20 respectively functions as an AND logic gate circuit, an OR logic gate circuit, or an XOR logic gate circuit. After the integrated circuit designer hands over the designed photomask patterns to the maker of the semiconductor body 10, upper metal layers are then formed on the semiconductor body 10 based on the photomask patterns.

Please refer to FIG. 1 in conjunction with FIG. 2. FIG. 2 is a diagram showing traces routed within the synchronous regions 14 a, 14 b. In the synchronous region 14 a, a clock trace 22 a vertically crosses each functional circuit cell 18 a of the synchronous region 14 a. In addition, two power traces 24 a, 26 a also cross each functional circuit cell 18 a of the synchronous region 14 a. The power traces 24 a, 26 a are respectively used to provide operating voltages (a high voltage level Vdd and a low voltage level Vss for example) required by each functional circuit cell 18 a. Similarly, a clock trace 22 b and two power traces 24 b, 26 b vertically cross each functional circuit cell 18 b of the synchronous region 14 b. As shown in FIG. 2, power traces 24 a, 24 b, 26 a, 26 b are respectively located at both sides of the clock traces 22 a, 22 b so that noise transmitted by the clock traces 22 a, 22 b interfering with the clock signals is reduced. In other words, clock skew related to the clock signal is lessened.

As mentioned above, the semiconductor body 10 of the prior art integrated circuit is divided into synchronous regions 14 a, 14 b and a non-synchronous region 16. The functional circuit cells 18 a, 18 b, driven by the clock signals, are distributed in the synchronous regions 14 a, 14 b. That is, the prior art has to consider clock balance for controlling clock skew according to the geometric distribution of the synchronous regions 14 a, 14 b within the semiconductor body 10. However, based on the prior art, the semiconductor body 10 is required to define the synchronous regions 14 a, 14 b and the non-synchronous region 16. Therefore, when programming the semiconductor body 10 to perform a predetermined logic operation, the IC designer needs to consider the allocation of the synchronous regions 14 a, 14 b and the non-synchronous region 16 on the semiconductor body 10. It is obvious that the allocation of the synchronous regions 14 a, 14 b and the non-synchronous region 16 on the prior art semi-conductor body 10 is fixed. Therefore, it is impossible to elastically program traces routed among the transistors within the synchronous regions 14 a, 14 b and the non-synchronous region 16 for implementing another predetermined logic operation mentioned above.

Because the synchronous regions 14 a, 14 b and the non-synchronous region 16 on the semiconductor body 10 are defined according to a predetermined ratio, say, the ratio of transistors within the synchronous regions 14 a, 14 b to the transistors within the non-synchronous region 16, for respectively establishing the clocked logic circuits and the non-clocked logic circuits, the application field of the semiconductor body 10 is limited by the fixed allocation of the synchronous regions 14 a, 14 b and the non-synchronous region 16. That is, the application elasticity of the prior art semiconductor body 10 is bad.

SUMMARY OF INVENTION

It is therefore a primary objective of the claimed invention to provide a method of programming basic units randomly positioned on a semiconductor body for forming either a clocked logic circuit or a non-clocked logic circuit according to different requirements.

Briefly summarized, a preferred embodiment discloses a method of fabricating an integrated circuit. The integrated circuit has a semiconductor body. The claimed method includes forming a plurality of basic units on the semiconductor body, each of the basic units having an identical device characteristic, and forming at least a layout layer to program the basic units for generating a clocked logic circuit and a non-clocked logic circuit without placing restrictions on positions of the clocked logic circuit and the non-clocked logic circuit on the semiconductor body.

According to the preferred embodiment, another claimed method of fabricating the integrated circuit includes forming a plurality of basic units on the semiconductor body, each of the basic units having a plurality of first transistors cascaded in a series and a plurality of second transistors cascaded in a series, and forming at least a layout layer to program traces among the first transistors and the second transistors of at least a basic unit for controlling the basic unit to form either a clocked logic circuit or a non-clocked logic circuit.

The preferred embodiment discloses an integrated circuit, and the claimed integrated circuit includes a semiconductor body for positioning a plurality of basic unit, each of the basic units having an identical device characteristic; a clocked logic circuit formed on the semiconductor body, the clocked logic circuit being formed by at least a basic unit; and a non-clocked logic circuit formed on the semiconductor body, the non-clocked logic circuit being formed by at least a basic unit. The semiconductor body does not limit locations of the clocked logic circuit and the non-clocked logic circuit formed on the semiconductor body.

According to the preferred embodiment, another claimed integrated circuit includes a semiconductor body for positioning a plurality of basic units, each of the basic units having a plurality of first transistors cascaded in a series and a plurality of second transistors cascaded in a series, a clocked logic circuit formed on the semiconductor body, and a non-clocked logic circuit formed on the semiconductor. The clocked logic circuit is formed by at least a basic unit, and the non-clocked logic circuit is formed by at least a basic unit.

The claimed method forms a plurality of basic units on a semiconductor body, wherein the allocation of basic units on the semiconductor body is not divided into a synchronous region and a non-synchronous region. Then, the method according to the present invention dynamically determines how many basic units are required to form clocked logic circuits and how many basic units are needed to form non-clocked logic circuits according to functionality of different integrated circuits. Therefore, the same semiconductor bodies are easily programmed by metal layers to produce different integrated circuits.

These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art at reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing a prior art semiconductor body of an integrated circuit.

FIG. 2 is a diagram showing traces routed within the synchronous regions.

FIG. 3 is a diagram showing a semiconductor body according to the present invention.

FIG. 4 is a diagram of a basic unit shown in FIG. 3.

FIG. 5 is a diagram illustrating inverters established by the basic unit according to the present invention.

FIG. 6 is an equivalent circuit diagram of the inverters shown in FIG. 5.

FIG. 7 is a diagram illustrating an NOR gate established by the basic unit according to the present invention.

FIG. 8 is an equivalent circuit diagram of the NOR gate shown in FIG. 7.

FIG. 9 is a diagram illustrating a flip-flop established by basic units according to the present invention.

FIG. 10 is an equivalent circuit diagram of the flip-flop shown in FIG. 9.

FIG. 11 is a diagram of another basic unit according to the present invention.

FIG. 12 is a diagram illustrating a multiplexer established by the basic unit shown in FIG. 11.

FIG. 13 is an equivalent circuit diagram of the multiplexer shown in FIG. 12.

DETAILED DESCRIPTION

Please refer to FIG. 3, which is a diagram showing a semiconductor body 40 according to the present invention. The semiconductor body 40 has a plurality of basic units 42. In the preferred embodiment, the basic units 42 are positioned on the semiconductor body 40 according to a matrix format for acquiring greater density. In other words, the area required to accommodate the basic units 42 is reduced to further shrink size of the corresponding integrated circuit. It is well-known that a semiconductor foundry fabricates the semiconductor body 40 in advance. An integrated circuit designer is then capable of designing photomask patterns for traces routed among the basic units 42. In the end, according to the photomask patterns designed by the integrated circuit designer, the semiconductor foundry forms at least a metal layer upon the semiconductor body 40 to position conductive wires routed among the basic units 42. Therefore, a single basic unit 42 or a group of basic units 42 can be programmed to make the integrated circuit capable of performing a predetermined logic operation according to the design defined by the IC designer.

Please refer to FIG. 4, which is a diagram of the basic unit 42 shown in FIG. 3. In the preferred embodiment, six transistors 44 a, 44 b, 44 c, 46 a, 46 b, 46 c are positioned within the basic unit 42, wherein transistors 44 a, 44 b, 44 c are PMOS transistors, and transistors 46 a, 46 b, 46 c are NMOS transistors. In addition, transistors 44 a, 44 b, 44 c are cascaded in a series, and transistors 46 a, 46 b, 46 b are cascaded in a series as well. As shown in FIG. 3, a plurality of basic units 42 are allocated on the semiconductor body 40. It is obvious from FIG. 4 that one basic unit 42 only contains transistors 44 a, 44 b, 44 c, 46 a, 46 b, 46 c. The allocation of basic units 42 is not divided into a synchronous region and a non-synchronous region as the prior art does. In other words, the randomly positioned basic units 42 according to the present invention are programmed to establish either a clocked logic circuit or a non-clocked logic circuit through metal layers. Therefore, when the basic units 42 are programmed, they are not divided into two groups (a synchronous region and a non-synchronous region for example) according to their locations. That is, no restriction is placed on positions of the clocked logic circuit and the non-clocked logic circuit on the semiconductor body when the basic units 42 are programmed to form the clocked logic circuit and the non-clocked logic circuit. Concerning the clocked logic circuit, it can be a flip-flop or a latch. With regard to the non-clocked logic circuit, it can function as a specific logic gate or a look-up table.

In the preferred embodiment, gates, sources, and drains of the transistors 44 a, 44 b, 44 c correspond to a plurality of programming nodes N₁, N₂, N₃, N₄, N₅, N₆, N₇. In addition, gates, sources, and drains of the transistors 46 a, 46 b, 46 c also correspond to a plurality of programming nodes N₈, N₉, N₁₀, N₁₁, N₁₂, N₁₃, N₁₄. Therefore, the logic operation run by the basic unit 42 is programmed and defined through the programming nodes N₁–N₁₄. Please refer to FIG. 5 in conjunction with FIG. 6. FIG. 5 is a diagram illustrating inverters 48 a, 48 b established by the basic unit 42 according to the present invention, and FIG. 6 is an equivalent circuit diagram of the inverters 48 a, 48 b shown in FIG. 5.

For the inverters 48 a, 48 b shown in FIG. 5, the programming node N₁ is electrically connected to the programming node N₈, the programming node N₂ is electrically connected to the programming node N₉, the programming node N₄ is electrically connected to the programming node N₁₁, the programming node N₅ is electrically connected to the programming node N₁₂, the programming node N₃ is electrically connected to a high voltage level (V_(dd) for example), and the programming node N₁₀ is electrically connected to a low voltage level (GND for example) through routing traces provided by at least a metal layer. In addition, programming nodes N₁, N₈ correspond to an output port OUT₁, programming nodes N₂, N₉ correspond to an input port IN₁, programming nodes N₄, N₁₁ correspond to an input port IN₂, and programming nodes N₅, N₁₂ correspond to an output port OUT₂.

Concerning the inverter 48 a, the transistor 46 a within the inverter 48 a is turned on, and the transistor 44 a is turned off when the input port IN₁ is driven by a high voltage level (V_(dd) for example). In other words, the voltage level of the output port OUT₁ approaches a low voltage level (GND for example). On the contrary, the transistor 44 a within the inverter 48 a is turned on, and the transistor 46 a is turned off when the input port IN₁ is driven by a low voltage level (GND for example). That is, the voltage level of the output port OUT₁ approaches a high voltage level (V_(dd) for example). Therefore, an equivalent circuit representing the inverter 48 a is shown in FIG. 6.

For the inverter 48 b, it has functionality identical to that of the inverter 48 a. When the input port IN₂ is driven by a high voltage level (V_(dd) for example), the transistor 46 b within the inverter 48 b is turned on, and the transistor 44 b remains off. In other words, the voltage level of the output port OUT₂ approaches a low voltage level (GND for example). On the contrary, the transistor 44 b within the inverter 48 b is turned on, and the transistor 46 b remains off when the input port IN₂ is driven by a low voltage level (GND for example). Therefore, the voltage level of the output port OUT₂ approaches a high voltage level (V_(dd) for example). Similarly, an equivalent circuit representing the inverter 48 a is shown in FIG. 6. From the above description, the basic units 42 according to the present invention are capable of establishing any non-clocked logic circuits on the semiconductor body 42 with the help of the routing traces programmed by metal layers.

Please refer to FIG. 7 in conjunction with FIG. 8. FIG. 7 is a diagram illustrating an NOR gate 50 established by the basic unit 42 according to the present invention, and FIG. 8 is an equivalent circuit diagram of the NOR gate 50 shown in FIG. 7. For programming the basic unit 42 to establish the NOR gate 50 shown in FIG. 7, at least a metal layer is utilized to implement required routing traces. Consequently, the programming node N₁ is electrically connected to a high voltage level (V_(dd) for example), the programming node N₈ is electrically connected to a low voltage level (GND for example), the programming node N₂ is electrically connected to the programming node N₉, the programming node N₄ is electrically connected to the programming node N₁₁, the programming node N₆ is electrically connected to the programming node N₁₃, and the programming node N₇ is electrically connected to the programming nodes N₁₀, N₁₄. In addition, programming nodes N₂, N₉ correspond to an input port IN₁, programming nodes N₄, N₁₁ correspond to an input port IN₂, programming nodes N₆, N₁₃ correspond to an input port IN₃, and programming nodes N₇, N₁₀, N₁₄ correspond to an output port OUT.

Because all of the transistors 46 a, 46 b, 46 c are NMOS transistors, the output port OUT is forced to correspond to the low voltage level (GND for example) when one of the input ports IN₁, IN₂, IN₃ is driven by the high voltage level to turn on a corresponding transistor 46 a, 46 b, 46 c. However, the transistors 44 a, 44 b, 44 c are PMOS transistors and cascaded in a series. Therefore, the output port OUT is allowed to have a voltage level equaling the high voltage level (V_(dd) for example) only when all of the input ports IN₁, IN₂, IN₃ are driven by the low voltage level (GND for example). At this time, all of the transistors 44 a, 44 b, 44 c are turned on, and the transistors 46 a, 46 b, 46 c are switched off. An equivalent circuit standing for the NOR gate 50 is shown in FIG. 8. It is clear from the above description that the basic units 42 according to the present invention are capable of establishing any non-clocked logic circuits on the semiconductor body 42 with the help of the routing traces programmed by metal layers.

In the preferred embodiment, the basic unit 42 has 6 transistors 44 a, 44 b, 44 c, 46 a, 46 b, 46 c. As mentioned above, one basic unit 42 and appropriate routing traces are capable of building a circuit structure corresponding to the inverter 48 a, 48 b or the NOR gate 50. However, it is impossible to utilize just one basic unit and appropriate routing traces to establish all kinds of logic circuits. Therefore, the method according to the present invention makes use of a plurality of basic units and appropriate routing traces to build a complicated logic circuit such as a flip-flop.

Please refer to FIG. 9 in conjunction with FIG. 10. FIG. 9 is a diagram illustrating a flip-flop 60 established by basic units 42 a, 42 b, 42 c according to the present invention, and FIG. 10 is an equivalent circuit diagram of the flip-flop 60 shown in FIG. 9. Concerning the basic unit 42 a shown in FIG. 9, the programming node N₁ is electrically connected to a high voltage level (V_(dd) for example), the programming node N₈ is electrically connected to a low voltage level (GND for example), the programming node N₂ is electrically connected to the programming node N₉, the programming node N₄ is electrically connected to the programming node N₁₃, the programming node N₆ is electrically connected to the programming node N₁₁, and the programming node N₇ is electrically connected to the programming node N₁₄ with the help of the traces routed on at least a metal layer.

With regard to another basic unit 42 b, the programming node N₁ is electrically connected to the programming node N₈, the programming node N₂ is electrically connected to the programming node N₉, the programming node N₃ is electrically connected to a high voltage level (V_(dd) for example), the programming node N₁₀ is electrically connected to a low voltage level (GND for example), the programming node N₄ is electrically connected to the programming node N₁₁, and the programming node N₅ is electrically connected to the programming node N₁₂ with the help of the traces routed on at least a metal layer.

Concerning the last basic unit 42 c, the programming node N₁ is electrically connected to a high voltage level (V_(dd) for example), the programming node N₈ is electrically connected to a low voltage level (GND for example), the programming node N₂ is electrically connected to the programming node N₉, the programming node N₄ is electrically connected to the programming node N₁₃, the programming node N₆ is electrically connected to the programming node N₁₁, and the programming node N₇ is electrically connected to the programming node N₁₄ with the help of the traces routed on at least a metal layer. In addition, basic units 42 a, 42 b, 42 c are electrically connected through proper routing traces. That is, programming nodes N₂, N₉ of the basic unit 42 a are electrically connected to programming nodes N₁, N₈ of the basic unit 42 b and programming nodes N₇, N₁₄ of the basic unit 42 c, programming nodes N₅, N₁₂ of the basic unit 42 a are electrically connected to programming nodes N₂, N₉ of the basic unit 42 b, programming nodes N₄, N₁₁ of the basic unit 42 b are electrically connected to programming nodes N₅, N₁₂ of the basic unit 42 c, and programming nodes N₅, N₁₂ of the basic unit 42 b are electrically connected to programming nodes N₂, N₉ of the basic unit 42 c.

In addition, a clock signal CLK is respectively inputted into the programming node N₆ of the basic unit 42 a and the programming node N₁₃ of the basic unit 42 c, and another clock signal

-   CLK,     which is an inverted signal of the clock signal CLK, is inputted     into the programming node N₁₃ of the basic unit 42 a and the     programming node N₆ of the basic unit 42 c. The clock signal CLK and     the clock signal -   CLK     are used for controlling transistor switches formed by the NMOS     transistors and PMOS transistors.

As shown in FIG. 9, the basic units 42 a, 42 c have similar routing designs. That is, the basic unit 42 a is used to establish the circuit unit 62 shown in FIG. 10, and the basic unit 42 c is used to establish the circuit unit 64 shown in FIG. 10. For the basic unit 42 a, the programming nodes N₇, N₁₄ function as an input port IN of the flip-flop 60. With regard to the basic unit 42 c, the programming nodes N₂, N₄ function as an output port OUT of the flip-flop 60. Taking the circuit structure corresponding to the basic unit 42 a for example, it is obvious from the circuit structures of the inverters 48 a, 48 b shown in FIG. 5 that the transistors 44 a, 46 a are used to establish an inverter 65.

In addition, the gate (the programming node N₁₃) of the transistor 46 c is connected to the gate (the programming node N₄) of the transistor 44 b, and the gate (the programming node N₆) of the transistor 44 c is connected to the gate (the programming node N₁₁) of the transistor 46 b. The voltage level of the clock signal CLK, therefore, is used to turn on one of the transistor switch 66 formed by transistors 44 c, 46 c and the transistor switch 67 formed by the transistors 44 b, 46 b. That is, when the transistor switch 66 is turned on, the transistor switch 67 is turned off accordingly. On the other hand, when the transistor switch 67 is turned on, the transistor switch 66 is turned off accordingly. Similarly, it is known that basic unit 42 b within the flip-flop 60 is used to establish the inverter 68 corresponding to the circuit unit 62 and the inverter 69 corresponding to the circuit unit 64 according to the circuit structures of the inverters 48 a, 48 b shown in FIG. 5. As mentioned above, the basic units 42 according to the present invention, therefore, are capable of establishing any clocked logic circuits on the semiconductor body 42 with the help of the routing traces programmed by metal layers.

Please note that the basic unit 42 as shown in FIG. 4 only has 6 transistors 44 a, 44 b, 44 c, 46 a, 46 b, 46 c. However, the basic unit 42 according to the present invention is not limited to a fixed amount of transistors. That is, the basic unit 42 is allowed to include a plurality of transistors. Therefore, a single basic unit 42 or a group of basic units 42 can be programmed to perform a predetermined logic operation through metal layers. Please refer to FIGS. 11, 12, and 13. FIG. 11 is a diagram of another basic unit 70 according to the present invention. FIG. 12 is a diagram illustrating a multiplexer 76 established by the basic unit 70 shown in FIG. 11. FIG. 13 is an equivalent circuit diagram of the multiplexer 76 shown in FIG. 12. The basic unit 70 has 8 transistors 72 a, 72 b, 72 c, 72 d, 74 a, 74 b, 74 c, 74 d, wherein transistors 72 a, 72 b, 72 c, 72 d are PMOS transistors, and transistors 74 a, 74 b, 74 c, 74 d are NMOS transistors. In addition, transistors 72 a, 72 b, 72 c, 72 d are cascaded in a series, and transistors 74 a, 74 b, 74 c, 74 d are cascaded in a series as well. As shown in FIG. 3, the basic units 70 and the basic units 42 are positioned according to the same rule mentioned before. In other words, the allocation of the basic units 70 is not divided into a synchronous region and a non-synchronous region, and the basic units 70 are programmed to establish either a clocked logic circuit or a non-clocked logic circuit with the help of the metal layers. Similarly, gates, sources, and drains of the transistors 72 a, 72 b, 72 c, 72 d, 74 a, 74 b, 74 c, 74 d correspond to a plurality of programming nodes N₁–N₁₈. Therefore, the traces routed among the programming nodes N₁–N₈ are controlled to achieve the objective of programming functionality of the basic unit 70.

Concerning the basic unit 70 shown in FIG. 12, the programming nodes N₁, N₉ are electrically connected to a high voltage level (V_(dd) for example), programming nodes N₁₀, N₁₈ are electrically connected to a low voltage level (GND for example), the programming node N₂ is electrically connected to the programming node N₁₁, the programming node N₃ is electrically connected to the programming node N₁₂, the programming node N₄ is electrically connected to the programming node N₁₅, the programming node N₆ is electrically connected to the programming node N₁₃, the programming node N₇ is electrically connected to the programming node N₁₆, and the programming node N₈ is electrically connected to the programming node N₁₇. In addition, a selecting signal SEL is inputted into the programming node N₁₅, and another selecting signal

-   SEL,     which is an inverted signal of the selecting signal SEL, is inputted     to the programming node N₆. In the preferred embodiment, programming     nodes N₂, N₁₁ function as an input port IN₁, programming nodes     function as another input port IN₂, and programming nodes N₅, N₁₄     function as an output port OUT.

Transistors 72 a, 74 a are used to form the inverter 77 a shown in FIG. 13, and the programming nodes N₃, N₁₂ correspond to an output port of the inverter 77 a. Similarly, transistors 72 d, 74 d are used to form another inverter 77 b shown in FIG. 13, and the programming nodes N₇, N₁₆ correspond to an output port of the inverter 77 b. In addition, transistors 72 b, 74 b are used to establish the transistor switch 78 a shown in FIG. 13, and transistors 72 c, 74 c are used to establish another transistor switch 78 b shown in FIG. 13. Please note that the gate (the programming node N₁₅) of the transistor 74 c is connected to the gate (the programming node N₄) of the transistor 72 b, and the gate (the programming node N₆) of the transistor 72 c is connected to the gate (the programming node N₁₃) of the transistor 74 b. The selecting signal SEL, therefore, is capable of turning on one of the transistor switches 78 a, 78 b. That is, when the transistor switch 78 a is turned on, the peer transistor switch 78 b is turned off accordingly. Therefore, a signal inputted into the input port IN₁ is successfully outputted from the output port OUT. On the other hand, when the transistor switch 78 b is turned on, the peer transistor switch 78 a is turned off accordingly. Therefore, a signal inputted into the input port IN₂ is successfully outputted from the output port OUT. In other words, the multiplexer 76 functions as a 2:1 multiplexer.

The basic unit 70 includes 8 transistors, and it still can be programmed to establish a non-clocked logic circuit on the semiconductor body 40 through the traces routed on the metal layers. For the circuit structure shown in FIG. 9, it is easily implemented with 3 basic units 70. Therefore, the basic units 70 can be programmed to establish a clocked logic circuit on the semiconductor body 40 as well through the traces routed on the metal layers. To sum up, the present invention does not limit the number of transistors within a basic unit to a fixed value. That is, either a single basic unit or a group of basic units can be used to establish any clocked logic circuits or non-clocked logic circuits with the help of traces properly routed on the metal layers.

In contrast to the prior art, the method of fabricating an integrated circuit according to the present invention forms a plurality of basic units on a semiconductor body, wherein the allocation of basic units on the semiconductor body is not divided into a synchronous region and a non-synchronous region. Then, the method according to the present invention dynamically determines how many basic units are required to form clocked logic circuits and how many basic units are needed to form non-clocked logic circuits according to functionality of different integrated circuits. In other words, the method according to the present invention is capable of adjusting an amount of basic units corresponding to the clocked region and an amount of transistors corresponding to the non-clocked region. Therefore, the same semiconductor bodies are easily programmed by metal layers to produce different integrated circuits.

Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. 

1. A method of fabricating an integrated circuit, the integrated circuit having a semiconductor body, the method comprising following steps: (a) forming a plurality of basic units on the semiconductor body, each of the basic units having an identical structure; and (b) forming at least a layout layer to program the basic units for generating a clocked logic circuit and a non-clocked logic circuit without placing restrictions on positions of the clocked logic circuit and the non-clocked logic circuit on the semiconductor body; wherein the clocked logic circuit comprises at least two of the basic units of which at least one of the at least two basic units is programmed to be isolated from a clock feed.
 2. The method of claim 1 wherein step (a) forms at least a transistor within each of the basic units.
 3. The method of claim 2 wherein the transistor is an MOS transistor.
 4. The method of claim 1 wherein step (b) utilizes the layout layer to program a plurality of basic units for generating the clocked logic circuit.
 5. The method of claim 1 wherein step (b) utilizes the layout layer to program a basic unit for generating the non-clocked logic circuit.
 6. The method of claim 1 wherein step (b) utilizes the layout layer to program a plurality of basic units for generating the non-clocked logic circuit.
 7. The method of claim 1 wherein step (a) forms at least a PMOS transistor and at least an NMOS transistor within each of the basic units.
 8. An integrated circuit comprising: a semiconductor body for positioning a plurality of basic units, each of the basic units having an identical structure; a clocked logic circuit formed on the semiconductor body, the clocked logic circuit being formed by at least one of the basic units; and a non-clocked logic circuit formed on the semiconductor body, the non-clocked logic circuit being formed by at least one of the basic units; wherein the clocked logic circuit comprises at least two of the basic units of which at least one of the at least two basic units is programmed to be isolated from a clock feed.
 9. The integrated circuit of claim 8 wherein each of the basic units comprises at least a transistor.
 10. The integrated circuit of claim 9 wherein the transistor is a MOS transistor.
 11. The integrated circuit of claim 8 wherein each of the basic units comprises at lease a PMOS transistor and at least an NMOS transistor.
 12. A method of fabricating an integrated circuit, the method comprising the following steps: forming a plurality of basic units on a semiconductor body, each of the basic units having a first row of transistors cascaded in a series and a second row of transistors cascaded in a series; forming at least a layout layer to program traces among the first row of transistors and the second row of transistors of at least a first basic unit; and forming a clocked logic circuit by at least two of the basic units of which at least one of the at least two basic units is programmed to be isolated from a clock feed.
 13. The method of claim 12 wherein forming a clocked logic circuit comprises: programming at least one of the basic units to form a plurality of logic gates isolated from the clock feed; and programming at least one of the other basic units to receive the clock feed, such that at least one of the transistors in the basic unit is connected to the clock feed.
 14. The method of claim 12 further comprising: while programming at least one of the basic units isolated from the clock feed, forming at least one logic signal input port by connecting gates of at least one transistor of the first row and at least one transistor of the second row, and forming at least one logic signal output port by connecting drains of at least one transistor of the first row and at least one transistor of the second row, and programming at least one of the other basic units to receive the clock feed by programming at least one transistor in the basic unit such that the at least one transistor have a gate connected to receive the clock gate, and a drain or a source connected to the logic signal input port or the logic output port.
 15. An integrated circuit comprising: a semiconductor body for positioning a plurality of basic units, each of the basic units having a first row of first transistors cascaded in a series and a second of second transistors cascaded in a series; a layout layer comprising traces among the first row of transistors and the second row of transistors of at least one of the basic units; and a clocked logic circuit comprising at least two of the basic units of which at least one of the at least two basic units is programmed to be isolated from a clock feed by the layout layer.
 16. The integrated circuit of claim 15 wherein the layout layer further comprises traces so that a gate of a first transistor of the first row of transistors is coupled to a gate of a first transistor of the second row of transistors, a gate of a second transistor of the first row of transistors is coupled to a gate of a third transistor of the second row of transistors, and a gate of a third transistor of the first row of transistors is coupled to a gate of a second transistor of the second row, a source of the first transistor of the first row of transistors is coupled to a high voltage source, a source of the first transistor of the second row of transistors is coupled to ground, a source of the second transistor of the first row of transistors is coupled to a source of the second transistor of the second row of transistors, a source of the third transistor of the first row of transistors is coupled to a source of the third transistor of the second row of transistors, a drain of the third transistor of the first row of transistors is coupled to a drain of the third transistor of the second row of transistors, the gate of the third transistor of the first row of transistors is coupled to a system clock, and the gate of the third transistor of the second row of transistors is coupled to an inversion of the system clock.
 17. The integrated circuit of claim 15 wherein the first row of transistors of each basic unit is PMOS transistors, and the second row of transistors of each basic unit is NMOS transistors. 